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| EN25P64 Purpose Eon Silicon Solution Inc. (hereinafter called "Eon") is going to provide its products' top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon's product family. Eon products' New Top Marking cFeon Top Marking Example: cFeon Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX Continuity of Specifications There is no change to this data sheet as a result of offering the device as an Eon product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Eon continues to support existing part numbers beginning with "Eon" and "cFeon" top marking. To order these products, during the transition please specify "Eon top marking" or "cFeon top marking" on your purchasing orders. For More Information Please contact your local sales office for additional information about Eon memory solutions. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 EN25P64 64 Megabit Uniform Sector, Serial Flash Memory FEATURES * Single power supply operation - Full voltage range: 2.7-3.6 volt * Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 * 64 M-bit Serial Flash - 64 M-bit/8192 K-byte/32768 pages - 256 bytes per programmable page * High performance - 100MHz clock rate * Low power consumption - 12 mA typical active current - 1 A typical power down current * Uniform Sector Architecture: - One hundred twenty-eight 64-Kbyte sectors * Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin * High performance program/erase speed Byte program time: 7s typical Page program time: 1.5ms typical Sector erase time: 800ms typical Chip erase time: 50 Seconds typical * Lockable 512byte OTP security sector * Minimum 100K endurance cycle * Package Options - 16 pins SOP 300mil body width - All Pb-free packages are RoHS compliant * Industrial temperature Range GENERAL DESCRIPTION The EN25P64 is a 64M-bit (8192K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25P64 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25P64 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Figure.1 CONNECTION DIAGRAMS 16 - LEAD SOP Figure 2. BLOCK DIAGRAM This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 3 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 SIGNAL DESCRIPTION Serial Data Input (DI) The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin. Serial Data Output (DO) The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Hold (HOLD#) The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). The hold function can be useful when multiple devices are sharing the same SPI signals. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (BP0, BP1and BP2) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. Table 1. PIN Names Symbol CLK DI DO CS# WP# HOLD# Vcc Vss Pin Name Serial Clock Input Serial Data Input Serial Data Output Chip Enable Write Protect Hold Input Supply Voltage (2.7-3.6V) Ground This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 4 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 MEMORY ORGANIZATION The memory is organized as: 8,388,608 bytes Uniform Sector Architecture One hundred twenty-eight 64-Kbyte sectors 32768 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable but not Page Erasable. Table 2 Block Sector Architecture Sector 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 SECTOR SIZE (KByte) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 5 Address range 7F0000h - 7FFFFFh 7E0000h - 7EFFFFh 7D0000h - 7DFFFFh 7C0000h - 7CFFFFh 7B0000h - 7BFFFFh 7A0000h - 7AFFFFh 790000h - 79FFFFh 780000h - 78FFFFh 770000h - 77FFFFh 760000h - 76FFFFh 750000h - 75FFFFh 740000h - 74FFFFh 730000h - 73FFFFh 720000h - 72FFFFh 710000h - 71FFFFh 700000h - 70FFFFh 6F0000h - 6FFFFFh 6E0000h - 6EFFFFh 6D0000h - 6DFFFFh 6C0000h - 6CFFFFh 6B0000h - 6BFFFFh 6A0000h - 6AFFFFh 690000h - 69FFFFh 680000h - 68FFFFh 670000h - 67FFFFh 660000h - 66FFFFh 650000h - 65FFFFh 640000h - 64FFFFh 630000h - 63FFFFh 620000h - 62FFFFh 610000h - 61FFFFh 600000h - 60FFFFh 5F0000h - 5FFFFFh 5E0000h - 5EFFFFh 5D0000h - 5DFFFFh 5C0000h - 5CFFFFh 5B0000h - 5BFFFFh (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Rev. D, Issue Date: 2009/1/8 EN25P64 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 6 5A0000h - 5AFFFFh 590000h - 59FFFFh 580000h - 58FFFFh 570000h - 57FFFFh 560000h - 56FFFFh 550000h - 55FFFFh 540000h - 54FFFFh 530000h - 53FFFFh 520000h - 52FFFFh 510000h - 51FFFFh 500000h - 50FFFFh 4F0000h - 4FFFFFh 4E0000h - 4EFFFFh 4D0000h - 4DFFFFh 4C0000h - 4CFFFFh 4B0000h - 4BFFFFh 4A0000h - 4AFFFFh 490000h - 49FFFFh 480000h - 48FFFFh 470000h - 47FFFFh 460000h - 46FFFFh 450000h - 45FFFFh 440000h - 44FFFFh 430000h - 43FFFFh 420000h - 42FFFFh 410000h - 41FFFFh 400000h - 40FFFFh 3F0000h - 3FFFFFh 3E0000h - 3EFFFFh 3D0000h - 3DFFFFh 3C0000h - 3CFFFFh 3B0000h - 3BFFFFh 3A0000h - 3AFFFFh 390000h - 39FFFFh 380000h - 38FFFFh 370000h - 37FFFFh 360000h - 36FFFFh 350000h - 35FFFFh 340000h - 34FFFFh 330000h - 33FFFFh 320000h - 32FFFFh 310000h - 31FFFFh 300000h - 30FFFFh 2F0000h - 2FFFFFh 2E0000h - 2EFFFFh 2D0000h - 2DFFFFh 2C0000h - 2CFFFFh 2B0000h - 2BFFFFh 2A0000h - 2AFFFFh 290000h - 29FFFFh 280000h - 28FFFFh (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Rev. D, Issue Date: 2009/1/8 EN25P64 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 270000h - 27FFFFh 260000h - 26FFFFh 250000h - 25FFFFh 240000h - 24FFFFh 230000h - 23FFFFh 220000h - 22FFFFh 210000h - 21FFFFh 200000h - 20FFFFh 1F0000h - 1FFFFFh 1E0000h - 1EFFFFh 1D0000h - 1DFFFFh 1C0000h - 1CFFFFh 1B0000h - 1BFFFFh 1A0000h - 1AFFFFh 190000h - 19FFFFh 180000h - 18FFFFh 170000h - 17FFFFh 160000h - 16FFFFh 150000h - 15FFFFh 140000h - 14FFFFh 130000h - 13FFFFh 120000h - 12FFFFh 110000h - 11FFFFh 100000h - 10FFFFh 0F0000h - 0FFFFFh 0E0000h - 0EFFFFh 0D0000h - 0DFFFFh 0C0000h - 0CFFFFh 0B0000h - 0BFFFFh 0A0000h - 0AFFFFh 090000h - 09FFFFh 080000h - 08FFFFh 070000h - 07FFFFh 060000h - 06FFFFh 050000h - 05FFFFh 040000h - 04FFFFh 030000h - 03FFFFh 020000h - 02FFFFh 010000h - 01FFFFh 000000h - 00FFFFh This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 7 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 OPERATING FEATURES SPI Modes The EN25P64 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK. Figure 3. SPI Modes Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 8 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The WIP bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits. In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is protected form program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25P64 provides the following data protection mechanisms: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction completion or Bulk Erase (BE) instruction completion or The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 9 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 3 Protected Area Sizes Sector Organization Status Register Content BP2 BP1 BP0 Bit Bit Bit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Memory Content Protect Areas None Sector 126 to 127 Sector 124 to 127 Sector 120 to 127 Sector 112 to 127 Sector 96 to 127 Sector 64 to 127 All Addresses None 7E0000h-7FFFFFh 7C0000h-7FFFFFh 780000h-7FFFFFh 700000h-7FFFFFh 600000h-7FFFFFh 400000h-7FFFFFh 000000h-7FFFFFh Density(KB) None 128KB 256KB 512KB 1024KB 2048KB 4096KB 8192KB Portion None Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Hold Function The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low (as shown in Figure 4.). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low. If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are Don't Care. Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold condition. Figure 4. Hold Condition Waveform This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored. In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE, exact 24-bit address is a must, any less or more will cause the command to be ignored. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 4. Instruction Set Instruction Name Write Enable Write Disable Read Status Register Write Status Register Read Data Fast Read Page Program Sector Erase Bulk Erase Deep Power-down Release from Deep Power-down, and read Device ID Release from Deep Power-down Byte 1 Code 06h 04h 05h 01h 03h 0Bh 02h D8h C7h B9h (3) dummy dummy dummy (ID7-ID0) (S7-S0)(1) S7-S0 A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) dummy D7-D0 (Next byte) (D7-D0) Next byte continuous (Next Byte) continuous continuous continuous(2) Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes ABh This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Manufacturer/ Device ID Read Identification Enter OTP mode 90h 9Fh 3Ah dummy (M7-M0) dummy (ID15-ID8) 00h 01h (ID7-ID0) (M7-M0) (ID7-ID0) (5) (ID7-ID0) (M7-M0) (4) Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "( )" indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until CS# terminate the instruction. 3. The Device ID will repeat continuously until CS# terminate the instruction. 4. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction. 00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID. 5. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity. Table 5. Manufacturer and Device Identification OP Code ABh 90h 9Fh 1Ch 1Ch 2017h (M7-M0) (ID15-ID0) (ID7-ID0) 16h 16h Write Enable (WREN) (06h) The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. Figure 5. Write Enable Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 12 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Write Disable (WRDI) (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code "04h" into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, and Bulk Erase instructions. Figure 6. Write Disable Instruction Sequence Diagram Read Status Register (RDSR) (05h) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 7. Figure 7. Read Status Register Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 13 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 6. Status Register Bit Locations S7 SRP Status Register Protect 1 = status register write disable S6 S5 S4 BP2 S3 BP1 S2 BP0 S1 WEL S0 WIP (Write In Progress bit) 1 = write operation 0 = not in write operation volatile bit OTP_LOCK bit (note 1) 1 = OTP sector is protected (Block Protected (Block Protected (Block Protected (Write Enable bits) bits) bits) Latch) Reserved Reserved bits bits (note 2) (note 2) (note 2) 1 = write enable 0 = not write enable volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Note 1. In OTP mode, SRP bit is served as OTP_LOCK bit. 2. See the table "Protected Area Sizes Sector Organization". The status and control bits of the Status Register are as follows: WIP bit. The WIP bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure compatibility with future devices. SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. In OTP mode this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is protected form program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 14 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Write Status Register (WRSR) (01h) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI). The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the selftimed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3.. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1. Figure 8. Write Status Register Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 15 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Read Data Bytes (READ) (03h) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 9. Read Data Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 16 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Read Data Bytes at Higher Speed (FAST_READ) (0Bh) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 10. Fast Read Instruction Sequence Diagram Page Program (PP) (02h) The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 17 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3) is not executed. Figure 11. Page Program Instruction Sequence Diagram Sector Erase (SE) (D8h) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see Table 2.a and Table 2.b) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3) is not executed. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 18 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Figure 12. Sector Erase Instruction Sequence Diagram Bulk Erase (BE) (C7h) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. Chip Select (CS#) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 13. Bulk Erase Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 19 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Deep Power-down (DP) (B9h) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 9.). Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the Device ID of the device to be output on Serial Data Output (DO). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14 .Chip Select (CS#) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Deep Power-down Instruction Sequence Diagram Release from Deep Power-down and Read Device ID (RDI) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for reasons of backward compatibility, only, and should not be used for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction. When used only to release the device from the power-down state, the instruction is issued by driving the CS# pin low, shifting the instruction code "ABh" and driving CS# high as shown in Figure 15. After This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 20 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other instructions will be accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the CS# pin low and shifting the instruction code "ABh" followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 16. The Device ID value for the EN25P64 is listed in Table 5. The Device ID can be read continuously. The instruction is completed by driving CS# high. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2 (max), as specified in Table 11. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. Figure 15. Release Power-down Instruction Sequence Figure 16. Release Power-down / Device ID Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 21 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code "90h" followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Eon (1Ch) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 17. The Device ID values for the EN25P64 are listed in Table 5. If the 24-bit address is initially set to 000001h the Device ID will be read first Figure 17. Read Manufacturer / Device ID Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 22 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Read Identification (RDID) (9Fh) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte , and the memory capacity of the device in the second byte . Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction should not be issued while the device is in Deep Power down mode. The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock . The instruction sequence is shown in Figure 18. The Read Identification (RDID) instruction is terminated by driving Chip Select High at any time during data output. When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 18. Read Identification (RDID) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 23 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Enter OTP Mode (3Ah) This Flash has a extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read, program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 127 respectively, SRP bit becomes OTP_LOCK bit and can be reading by RDSR command. Program / Erase command will be disabled when OTP_LOCK is `1' WRSR command will ignore the input data and program LOCK_BIT to 1. User must clear the protect bits before enter OTP mode. OTP sector can only be program and erase when LOCK_BIT equal `0' and BP [2:0] = `000'. In OTP mode, user can read other sectors, but program/erase other sectors only allowed when OTP_LOCK equal `0'. User can use WRDI (04h) command to exit OTP mode. Figure 19. Enter OTP Mode Table 7 Security Sector Address Sector 127 Sector Size 512 byte Address Range 7FFE00h - 7FFFFFh Note: The OTP sector is mapping to sector 127 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Power-up Timing Figure 20. Power-up Timing Table 8. Power-Up Timing and Write Inhibit Threshold Symbol tVSL(1) tPUW(1) VWI(1) VCC(min) to CS# low Time delay to Write instruction Write Inhibit Voltage Parameter Min. 10 1 1 10 2.5 Max. Unit s ms V Note: 1.The parameters are characterized only. 2. VCC (max.) is 3.6V and VCC (min.) is 2.7V INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 25 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 9. DC Characteristics (Ta = - 40C to 85C; VCC = 2.7-3.6V) Symbol Parameter Test Conditions Min. Max. Unit ILI ILO ICC1 ICC2 Input Leakage Current Output Leakage Current Standby Current Deep Power-down Current CS# = VCC, VIN = VSS or VCC CS# = VCC, VIN = VSS or VCC CLK = 0.1 VCC / 0.9 VCC at 100MHz, DQ = open CLK = 0.1 VCC / 0.9 VCC at 75MHz, DQ = open CLK = 0.1 VCC / 0.9 VCC at 33MHz, DQ = open CS# = VCC CS# = VCC CS# = VCC CS# = VCC - 0.5 0.7VCC IOL = 1.6 mA IOH = -100 A VCC-0.2 2 2 5 5 20 15 12 15 15 15 15 0.2 VCC VCC+0.4 0.4 A A A A mA mA mA mA mA mA mA V V V V ICC3 Operating Current (READ) ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH Operating Current (PP) Operating Current (WRSR) Operating Current (SE) Operating Current (BE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Table 10. AC Measurement Conditions Symbol Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. CL = 20 pF when CLK=100MHz, CL = 30 pF when CLK=75MHz Min. 20/30 Max. Unit pF CL 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC ns V V V VCC / 2 Figure 21. AC Measurement I/O Waveform This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 11. 100MHz AC Characteristics (Ta = - 40C to 85C; VCC = 2.7-3.6V) Symbol FR fR tCH 1 Alt fC Parameter Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Serial Clock Frequency READ instruction Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time (Slew Rate) Serial Clock Fall Time (Slew Rate) Min D.C. D.C. 4 4 0.1 0.1 5 5 5 5 50 Typ Max 100 66 Unit MHz MHz ns ns V / ns V / ns ns ns ns ns ns tCL1 tCLCH2 tCHCL tSLCH tCHSH tSHCH tCHSL tSHSL tSHQZ tCLQX tDVCH tCHDX tHLCH tHHCH tCHHH tCHHL tHLQZ tHHQX tCLQV tWHSL3 tSHWL3 tDP 2 2 2 2 2 tCSS CS# Active Setup Time CS# Active Hold Time CS# Not Active Setup Time CS# Not Active Hold Time tCSH tDIS tHO tDSU tDH CS# High Time Output Disable Time Output Hold Time Data In Setup Time Data In Hold Time HOLD# Low Setup Time ( relative to CLK ) HOLD# High Setup Time ( relative to CLK ) HOLD# Low Hold Time ( relative to CLK ) HOLD# High Hold Time ( relative to CLK ) 6 0 2 5 5 5 5 5 6 6 8 20 100 3 3 1.8 10 1.5 0.8 50 15 5 2 80 ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ms ms s s tHZ tLZ tV HOLD# Low to High-Z Output HOLD# High to Low-Z Output Output Valid from CLK Write Protect Setup Time before CS# Low Write Protect Hold Time after CS# High CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature read CS# High to Standby Mode with Electronic Signature read Write Status Register Cycle Time Page Programming Time Sector Erase Time 64KB sectors Bulk Erase Time tRES1 2 tRES2 2 tW tPP tSE tBE Note: 1. TCLKH + TCLKL must be greater than or equal to 1/ FCLK 2. Value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write status Register instruction when Sector Protect Bit is set at 1. 4. VCC = 3.0-3.6V for 100MHz operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 12. 75MHz AC Characteristics (Ta = - 40C to 85C; VCC = 2.7-3.6V) Symbol FR fR tCH 1 Alt fC Parameter Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Serial Clock Frequency READ instruction Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time (Slew Rate) Serial Clock Fall Time (Slew Rate) Min D.C. D.C. 6 6 0.1 0.1 5 5 5 5 50 Typ Max 75 66 Unit MHz MHz ns ns V / ns V / ns ns ns ns ns ns tCL1 tCLCH2 tCHCL tSLCH tCHSH tSHCH tCHSL tSHSL tSHQZ tCLQX tDVCH tCHDX tHLCH tHHCH tCHHH tCHHL tHLQZ tHHQX tCLQV tWHSL3 tSHWL3 tDP 2 2 2 2 2 tCSS CS# Active Setup Time CS# Active Hold Time CS# Not Active Setup Time CS# Not Active Hold Time tCSH tDIS tHO tDSU tDH CS# High Time Output Disable Time Output Hold Time Data In Setup Time Data In Hold Time HOLD# Low Setup Time ( relative to CLK ) HOLD# High Setup Time ( relative to CLK ) HOLD# Low Hold Time ( relative to CLK ) HOLD# High Hold Time ( relative to CLK ) 6 0 2 5 5 5 5 5 6 6 6 20 100 3 3 1.8 10 1.5 0.8 50 15 5 2 80 ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ms ms s s tHZ tLZ tV HOLD# Low to High-Z Output HOLD# High to Low-Z Output Output Valid from CLK Write Protect Setup Time before CS# Low Write Protect Hold Time after CS# High CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature read CS# High to Standby Mode with Electronic Signature read Write Status Register Cycle Time Page Programming Time Sector Erase Time 64KB sectors Bulk Erase Time tRES1 2 tRES2 2 tW tPP tSE tBE Note: 1. TCLKH + TCLKL must be greater than or equal to 1/ FCLK 2. Value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write status Register instruction when Sector Protect Bit is set at 1. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 28 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Figure 22. Serial Output Timing Figure 23. Input Timing Figure 24. Hold Timing This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 29 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 ABSOLUTE MAXIMUM RATINGS Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. Parameter Storage Temperature Plastic Packages Output Short Circuit Current1 Input and Output Voltage (with respect to ground) 2 Vcc Value -65 to +150 -65 to +125 200 -0.5 to +4.0 Unit mA V -0.5 to +4.0 V Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot Vss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below. RECOMMENDED OPERATING RANGES 1 Parameter Ambient Operating Temperature Industrial Devices Value Unit -40 to 85 Operating Supply Voltage Vcc Full: 2.7 to 3.6 V Notes: 1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Vcc +1.5V Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 30 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Table 13. DATA RETENTION and ENDURANCE Parameter Description Data Retention Time 125C Erase/Program Endurance -40 to 85 C 20 100k Years cycles Test Conditions 150C Min 10 Unit Years Table 14. CAPACITANCE ( VCC = 2.7-3.6V) Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Setup VIN = 0 VOUT = 0 Typ Max 6 8 Unit pF pF Note : Sampled only, not 100% tested, at TA = 25C and a frequency of 20MHz. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 31 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 PACKAGE MECHANICAL Figure 25. 16 LEAD SOP 300 mil MIN. A --A1 0.10 A2 2.25 C 0.20 D 10.10 E 10.00 E1 7.40 e --b 0.31 L 0.4 00 50 Note : 1. Coplanarity: 0.1 mm SYMBOL DIMENSION IN MM NOR MAX --2.65 0.20 0.30 --2.40 0.25 0.30 10.30 10.50 --10.65 7.50 7.60 1.27 ----0.51 --1.27 80 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 32 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 ORDERING INFORMATION EN25P64 75 F I P PACKAGING CONTENT (Blank) = Conventional P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE F = 16-pin 300mil SOP SPEED 100 = 100 Mhz 75 = 75 Mhz BASE PART NUMBER EN = Eon Silicon Solution Inc. 25P = 3V Serial Uniform-Sector FLASH 64 = 64 Megabit (8192K x 8) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 33 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 EN25P64 Revisions List Revision No Description A B Date C D Initial Release 2007/11/20 1. Remove C grade option of temperature range in page 130 and 2008/06/23 page 33 2. Update the Table 6. Status Register Bit Locations in page 14. 1. Add Eon products' New top marking "cFeon" information in page 1. 2008/12/18 2. Add the description "Serial Interface Architecture "and modify active current (typical) from 5mA to 12mA in page 2. 3. List the Note 4 for 90h command in Table 4 in page 12. 4. Update Table 6. Status Register Bit Locations in page 14. 5. Update Table 7 OTP Sector Address in page 24. 6. Add Note " Vcc (max) is 3.6V and Vcc (min) is 2.7V " in Table 8 in page 25. 7. Modify ICC3 from "Q = open" to " DQ = open " in Table 9 in page 26 8. Correct the typo "tCLH to tCH" "tCLL to tCL""tHHQZ to tHHQX" in Table 11 and Table 12 in page 27 and 28. 9. Modify Storage Temperature from "-65 to + 125" to "-65 to +150" in page 30 10. Delete Latch up Characteristics Table from version B. Modify tCSH to 50ns in Table 11 and 12 in page 27 and 28. 2009/1/8 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 34 (c)2004 Eon Silicon Solution, Inc., www.eonssi.com. Rev. D, Issue Date: 2009/1/8 |
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